Limits. Symbol. Parameter. Conditions. −40°C. +25°C. +85°C. Units. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. IL. Quiescent Device. VDD = V. Data sheet acquired from Harris Semiconductor. SCHSC – Revised September The CDUB types are supplied in lead hermetic dual-in- line. Order Number CD C National Semiconductor Corporation . This datasheet has been downloaded from: Datasheets for.
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Make the connections to an rc op-amp as shown in figure 3. What to do in the lab report Attach screen datasheeet for working frequencies, and for too high frequencies such that transitions between 0 and VDD are not complete. The capacitor will begin to charge. Application of CMOS logic. You are encouraged to write down your experience with this lab along with any feedback or suggestions.
Draw an equivalent circuit for the following wiring description using a CD However, the second transmission gate, which is now turned ON ensures that the previous logic level at Q is retained through the closed loop with the two-inverter cascade.
8. CMOS Logic Circuits — elec documentation
Capture a screen shot. Measure the output voltage of the second inverter and the voltage across the capacitor with the scope. You should take a total of three screenshots, one each, corresponding to each inverter output. Your output should look similar to figure Construct 3 inverters using a CD by making the following connections: Remember to ground the AI- terminals.
Remove all the connections to the ALD chip shown in the dashed box cd datasheet Figure 3. Output of first inverter.
Fairchild Semiconductor – datasheet pdf
Normally one would use anti-static mats and wrist straps when working with static cd datasheet electronics. Remember that chips 2 and 4 shown in Figure 8 need Vdd and Ground connections. What to do in lab report Show 3 screen shots of inverter outputs. The other two pairs are more general purpose.
Feedback You are encouraged to write down your experience with this lab along with any feedback datxsheet suggestions.
You do not have cd0407 draw a gate level schematic if you can determine the logic function implemented. You will see how the voltage transfer curve changes with VDD. Table Of Contents 8. Build a CMOS inverter.
You should see a graph similar to the one shown below in figure 4.
Try increasing the frequency and see at what frequency the inverter has trouble completing high to low and low to high transitions. Build a double transmission gate using a new CD chip as shown in Figure 6. It should look as shown below in Figure 5.
D is transmitted to the output Q through the first transmission gate and the two-inverter cascade. Make a pin-level wiring diagram for a transmission gate using a CD Connect pin 9, which serves as D input of the latch to DIO0.
Datasheeh, the input to cd4007 first inverter is close to the voltage at node C. That is going to be left as a bonus exercise. You should see that Dstasheet is also low.
Determine the logic function implemented datasheeh the following connections to a CD Set the function generator to output a Hz sine wave, 5vpp, 2. In which region cd datasheet it be operating when it is an open switch? You can download or view the data sheet cd datasheet or here.
Attach screen shots for different Cd datasheet. A steady high should appear. Output cd datasheet second inverter.
Attach screen shots for different VDD. Ids-Vds curves for multiple gate-to-source voltages Vgsfrom which we can observe linear and saturation operation regions. CMOS inverter schematic for voltage transfer measurement. First, assume the voltage at the input to the first inverter is zero.